Power supply protection arrangement

ABSTRACT

In a projection television receiver, a common switch mode power supply energizes the convergence circuits, and other load circuits of the projection television receiver. In normal operation, a switch couples a supply voltage produces in the common switch mode power supply to the convergence circuits. When, as a result of a fault, a supply current in the convergence circuits is excessive, the common switch mode power supply is decoupled from the convergence circuits and other load circuits remain energized and operative.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit, under 35 U.S.C. § 365 ofInternational Application PCT/US03/10278, filed Apr. 3, 2003, which waspublished in accordance with PCT Article 21(2) on Oct. 16, 2003 inEnglish and which claims the benefit of provisional application Ser. No.60/370,071, filed Apr. 4, 2002.

BACKGROUND OF THE INVENTION

The invention relates to a power supply protection arrangement of avideo display apparatus, for example, a projection television (TV)receiver.

The displayed image in, for example, a direct view TV receiver or in aprojection TV receiver having a cathode ray tube (CRT), may suffer fromelectron beam landing location errors such as geometrical andconvergence errors. It is known to correct such errors for a CRT using adynamic convergence arrangement. The amount of correction may varydynamically in a given deflection cycle, in accordance with the locationof the beam on the display screen.

In one prior art arrangement, to minimize manufacturing costs of adirect view TV receiver model and a projection TV receiver model, bothmodels shared the same chassis. The main deflection circuits werecommon. Direct view models used about 90% of the chassis. For economicreasons the main chassis power supply was sized for the direct viewmodel and a projection convergence power supply was added on for aprojection TV receiver model.

When, as a result of a fault, a supply current exceeds a predeterminedvalue, a threshold level of a protection detector is exceeded and causesthe dedicated convergence switch mode power supply to shut down. Troubleshooting convenience requires that the TV receiver show a picture whenthe convergence circuits have a fault. Thus, the rest of the TV receivercircuits including the deflection circuits remain energized andoperational. The convergence dedicated switch mode supply remains turnedoff until the projection TV receiver is turned off and then on, again,by a user.

In carrying out an inventive feature, a common switch mode power supplyenergizes the convergence circuits and the rest of the TV receivercircuits. Instead of using the prior art separate power suppliessolution, a fast acting latching power supply voltage disconnectarrangement for the convergence circuits is utilized. Such arrangementprovides a cost advantage.

FIG. 1 illustrates an example of a prior art power amplifier that drivesthe convergence winding in a CRT of the projection video display, shownin FIG. 3 of U.S. Pat. No. 4,961,032 in the name of Rodriguez-Cavazos,entitled, Dual Power Source Output Amplifier (the Rodriguez-Cavazospatent). The symbols and reference numerals in FIG. 1 are the same as inFIG. 3 of the Rodriguez-Cavazos patent except that a prime sign (′) isappended to each.

In FIG. 1, an amplifier 50′ comprises a differential amplifier 12′, abuffer 14′ and one output stage 16′. The differential amplifier 12′ isformed by transistors Q1′ and Q2′. An input waveform signal V_(IN)′ isconnected to the base of transistor Q1′. The collector of transistor Q1′is connected to a high voltage supply source of positive polarityvoltage +V_(H)′. The emitters of transistors Q1′ and Q2′ are connectedtogether, and through a resistor R1′, to a negative high supply voltage−V_(H)′. A parallel combination of sense resistors R21′ and R22′ areconnected to a deflection coil 24′ of a yoke Y1′ and the base oftransistor Q2′, for developing the sense voltage V_(S). A transistorQ11′ converts the output current at the collector of transistor Q2′ intoan output voltage across a load resistor R18′. Diodes D8′, D9′, D10′ andD11′ establish a biasing voltage for the buffer stage 14′, whichincludes transistors Q9′ and Q10′. The emitters of transistors Q9′ andQ10′ of the buffer stage drive the bases of transistors Q4′ and Q5′,respectively, through resistors R13′ and R14′, respectively. TransistorsQ4′ and Q5′ form class B output stage 16′. The emitters of transistorsQ4′ and Q5′ are connected to resistors R7′ and R8′, respectively. Theoutput voltage signal of the amplifier is generated at the junction ofresistors R7′ and R8′, which is connected to the coil 24′ of convergenceyoke Y1′.

Output stage 16′ provides high current. It needs to provide a highvoltage drive, during horizontal retrace, and a low voltage drive,outside horizontal retrace. Output stage 16′ compares dynamicallyvarying input signal V_(IN)′ to sense voltage V_(S) developed acrosscurrent sense resistors R21′ and R22′ that are coupled in series withthe convergence winding. Output stage 16′ generates the necessarycurrent to minimize any difference between the varying input signalV_(IN)′ and sense voltage V_(S)′.

If positive polarity voltage +V_(H)′ is turned off and, simultaneously,negative voltage supply −V_(H)′ is turned on, during a power-up orstart-up interval, transistors Q10′ and Q5′ will turn on at the limitConsequently, a current I_(Y1)′ in convergence yoke Y1′ having anexcessive magnitude flows also in sense resistors R21′ and R22′ thatcould damage them. Even a short-term overstress may cause anunacceptable sense resistor value change. A sense resistor value changecauses an uncompensated change in convergence correction gain thatdistorts the picture.

In a power supply embodying an inventive feature, a positive polarityvoltage that is analogous to voltage +V_(H)′ is turned on prior toturning on of negative voltage supply that is analogous to voltage−V_(H)′, during the power-up or start-up interval. Furthermore, a powersupply circuit breaking protection is employed that prevents excessivecurrent in the sense resistors, as a result of a failure in the feedbackloop.

SUMMARY OF THE INVENTION

A video display apparatus, embodying an inventive feature, including amain deflection circuit for generating a main deflection current in amain deflection winding to scan an electron beam on a screen of acathode ray tube. A first amplifier stage generates an auxiliarydeflection current in an auxiliary deflection winding to correct araster distortion. A power supply output transistor generates a firstpower supply current of a load circuit and a second power supply currentof the first amplifier stage. A sensor detects an occurrence a faultcondition in a current path of the power supply current of firstamplifier stage. A first power switch responsive to an output of thesensor for selectively reducing the second power supply current of thefirst amplifier stage, without interrupting the first power supplycurrent of the load circuit, when the fault condition occurs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a prior art power amplifier that drives a convergencewinding of a projection video display;

FIG. 2 a illustrates a prior art deflection system of a projectiontelevision receiver; and

FIG. 2 b illustrates a power supply having a protection arrangement,embodying an inventive feature, for the power amplifier of FIG. 2 a.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 a illustrates, in block diagram form, a conventional deflectionsystem 100 of a projection television receiver. Deflection system 100provides dynamic convergence. Three cathode ray tubes (CRT's), R, G andB produce electron beams that form a combined image 800 on a screen 700.The deflection field in each CRT is controlled in a similar way. Forexample, CRT G is equipped with a main horizontal deflection coil drivenby a horizontal deflection output stage 600 and with a main verticaldeflection coil driven by a vertical deflection amplifier 650,conventionally constructed. CRT G is also depicted with an auxiliaryhorizontal convergence coil 615 driven by a horizontal convergenceamplifier 610 and with an auxiliary vertical convergence coil 665 drivenby a vertical convergence amplifier stage or amplifier 660. Amplifier660 is energized by a positive supply voltage OUT+ and by a negativesupply voltage OUT−. Correction data stored in a memory, not shown, areapplied via a digital-to-analog (D/A) converter 312 and power amplifier660 to auxiliary vertical convergence coil 665.

Amplifier 660 may have a similar topology as the amplifier described inthe Rodriguez-Cavazos patent, shown in FIG. 1. For example, voltage OUT+of FIG. 2 a will be applied to the amplifier of FIG. 1 instead ofvoltage +V_(H)′ and voltage OUT− of FIG. 2 a will be applied to theamplifier of FIG. 1 instead of voltage −V_(H)′.

FIG. 2 b illustrates, in details, a power supply protection arrangement200, embodying an inventive feature. Similar symbols and numerals inFIGS. 2 a and 2 b indicate similar items or functions. A conventionalswitch mode power supply 400 of FIG. 2 b is coupled to a primary windingT1 a of a chopper transformer T1. A secondary winding T1b is coupled toa half wave rectifier D1 and a filter capacitor C1 for generating aregulated supply voltage V20VP of +20V, in a conventional manner.Winding T1 b is also coupled to a half wave rectifier D2 and a filtercapacitor C2 for generating a regulated supply voltage V20VN of −20V.

Voltage V20VP is applied via a pair of an inductor L1 and a capacitorC11 forming a low pass filter to an emitter of a power switch transistorQ1 a via a current sensing resistor R1. Inductor L1 and capacitor C11attenuate high frequency switching transients of switch mode powersupply 400. Similarly, voltage V20VN is applied via a pair of aninductor L2 and a capacitor C12 forming a low pass filter to an emitterof a power switch transistor Q2 a via a current sensing resistor R12.When conductive, transistor Q1 a applies voltage V20VP to, for example,a filter capacitor C5 to develop an output voltage OUT+ of +18V at apositive supply input terminal 660 a of convergence amplifier 660 ofdeflection system 100 of FIG. 2 a Similarly, when transistor Q2 a ofFIG. 2 b is conductive, voltage V20VN is applied to a filter capacitorC8 to develop an output voltage OUT− of −18V at a negative supply inputterminal of FIG. 2 a of convergence amplifier 660. On the other hand,when disabled, transistor Q1 a of FIG. 2 b decouples transformer T1 orvoltage V20VP from terminal 660 a of FIG. 2 a Similarly, when disabled,transistor Q2 a of FIG. 2 b decouples transformer T1 or voltage V20VNfrom terminal 660 b of FIG. 2 a. Transistor Q1 a of FIG. 2 b iscontrolled via a transistor Q1 b that are coupled in a Darlingtonconfiguration to form a switched Darlington transistor Q1. Similarly,transistor Q2 a is controlled via a transistor Q2 b that are coupled ina Darlington configuration to form a switched Darlington transistor Q2.

A pair of resistors R14 and R17 form a voltage divider for voltageV20VP. A pair of resistors R14 and R17 provide a discharge path toground for capacitor C1, when switch mode power supply 400 is turnedoff. Resistors R17 and R14 provide a 0.7V reference voltage acrossresistor R17 that is developed at the base of a transistor U1A. The baseof a transistor U1B is coupled to capacitor C9 to develop a base voltagein transistor U1B that is proportional to the average value of a supplyor load current IP. A sense resistors R1 develops a voltage VR1 that isindicative of a magnitude of supply current IP.

Transistors U1A and U1B are packaged to assure electrical matching andtemperature tracking to form a temperature compensated comparator. Acollector current is produced in transistor U1B, when the base voltageof transistor U1B is smaller than a threshold voltage determined by aratio of the values of resistors R21 and R15 and voltage V20VP.

Voltage VR1 is low pass filtered in a filter that includes a resistor R2and capacitor C9 for developing the base voltage of transistor U1B. Thetime constant of resistor R2 and capacitor C9 is selected for preventingshort term or transient overload such as an initial charging of outputfilter capacitor C5, during start-up, from falsely triggering thecomparator formed by transistors U1A and U1B. Such false triggering ofthe comparator formed by transistors U1A and U1B could cause anundesired power supply shut down, during a short term or transientoverload.

A similar arrangement is coupled to voltage V20VN and performs a similarfunction. Thus, a pair of NPN transistors U2A and U2B is analogous tothe pair of PNP transistors U1A and U1B, respectively. A pair ofresistors R15 and R21 is analogous to the pair of resistors R14 and R17,respectively. A resistor R12 is analogous to resistor R1. A resistor R11and capacitor C6 are analogous to resistor R2 and capacitor C9,respectively.

A latch 60 that is controlled by the collector current in each oftransistor U1B and U2B is formed by a pair of cross-coupled transistorsQ4 and Q5. The base of transistor Q4 is coupled to the collector oftransistor Q5 and the base of transistor Q5 is coupled to the collectorof transistor Q4. An emitter of transistor Q5 is coupled via an emitterresistor to the base of transistor Q1 b and to a series arrangement of aresistor R8 and a zener diode D3. A junction terminal 61 betweeninductor L1 and resistor R1 that develops a voltage level approximatelyequal to voltage V20P is coupled via an emitter resistor R19 to theemitter of transistor Q4 and via a collector resistor R5 to thecollector of transistor Q5 and to the base of transistor Q4.

When the average value of each of current IP and current IN is normal ornon-excessive, neither of voltage VR1 and VR12 is sufficient to turn onany of transistors U1B and U2B. Consequently, no collector current inproduced in any of transistors U1B and U2B. Therefore, transistors Q4and Q5 are turned off and remain in that state unless a fault conditionoccurs that causes any of current IP and current IN becomes excessive.

In the absence of a fault condition, no collector current is produced ineither transistor U1B or U2B. Therefore, latch 60 is not triggered andtransistors Q4 and Q5 are maintained turned off. The result is that thebase current of transistor Q1 flows through resistor R8 and diode D3causing base voltage 60 a to be at a sufficiently low level to maintaintransistor Q1 a in saturation. As a consequence of transistor Q1 a beingin saturation, voltage OUT+ is developed at a normal operation level. Atstart up, transistor Q1 will turn on when the voltage V20VP rises toabout 14 volts. Voltage 60 a is also developed in a capacitor C10 thatis coupled to the base of transistor Q1 b. After transistor Q1 turns on,its collector voltage OUT+rises to near +18V.

In carrying out an inventive feature, voltage OUT+ is coupled via azener diode D4 and a resistor R9 to the base of Darlington transistorQ2. Transistor Q2 a will turn on and be in saturation when thedifference between voltage OUT+ and voltage V20VN in capacitor C2, thatreaches −20V, exceeds about 29V. At this voltage level, base biascurrent for transistor Q2 starts to flow in diode D4 and resistor R9.Consequently voltage OUT− is maintained at a normal operation level of−18V. By using voltage OUT+ to control the turn on of transistor Q2, arequirement, discussed before with respect to the power amplifier of theRodriguez-Cavazos patent, that positive voltage OUT+ be developed beforenegative voltage OUT− is developed, is met.

When, as a result of fault, the average value of current IP in a currentpath that includes transistor Q1 a or current IN in a current path thatincludes transistor Q2 a is excessive, voltage VR1 or VR12 at a levelthat is sufficient to turn on transistor: U1B or U2B, respectively,appears across filter capacitor C9 or C6. Consequently, the collectorcurrent in transistor U1B or U2B, that is coupled via a resistor R3 or aresistor R7 to the base of transistor Q5 or Q4, respectively, willtrigger latch 60. Resistor R19 and a resistor R10 limit a transientcurrent that results from the rapid discharge of capacitor C10, duringthe transition of latch 60 to operation in a latching mode.

The latching mode in latch 60 is maintained by a current flowing fromterminal 61 and produced by voltage V20VP through transistors Q4 and Q5,resistor R8 and diode D3. The action of transistor Q4 and Q5 is similarto that of a silicon controlled switch (SCS). Transistors Q4 and Q5 areused to achieve a low sustaining current and a low cost. A siliconcontrolled rectifier (SCR) cannot be conveniently used because thecollector currents in transistors U1B and U2B that are required totrigger latch 60 are at opposite polarities. The saturation voltageacross transistors Q4 and Q5 is about 0.7V.

The switching state of Darlington transistors Q1 and Q2 are controlledby an output voltage 60 a of latch 60. Transistors Q4 and Q5, when latch60 operates in the latching mode, shunt the base emitter of Darlingtontransistor Q1. Therefore, a collector current in transistor Q5 increasesthe base voltage of transistor Q1 b in a manner to turn off transistorQ1 a. Thus, transformer T1 is decoupled from amplifier 660 of FIG. 2 a.Consequently, voltage OUT+is disabled.

A secondary winding T1 c of transformer T1 of FIG. 2 b is coupled to adiode 19 for generating a supply voltage VPS1 that energizes stages ofthe television receiver, for example, output stage 600 of FIG. 2 a. Whenvoltage OUT+ of FIG. 2 b and voltage OUT− are disabled, as a result of afault, as explained before, output stage 600 of FIG. 2 a remains,advantageously, operational. This facilitates service operation. Thus,transformer T1 forms a common power stage for both output stage 600 andamplifier 660 of FIG. 2 a.

During a transient overload condition such as, during start-up, whenfilter capacitors C5 and C6 of FIG. 2 b are charged, current IP intransistor Q1 or current IN is limited by a zener diode D5 and a zenerdiode D6, respectively, so that the maximum current ratings ofDarlington transistors Q1 and Q2 are not exceeded. Zener diode D5, forexample, is coupled between terminal 61 and the base of transistor Q1 b.

Capacitors across the base emitter-base terminals of the varioustransistors prevent turn on of the transistors by induced radiofrequency currents. Capacitors across the various zener diodes preventradio frequency radiation.

1. A video display apparatus, comprising: a main deflection circuit forgenerating a main deflection current in a main deflection winding toscan an electron beam on a screen of a cathode ray tube; a firstamplifier stage for generating an auxiliary deflection current in anauxiliary deflection winding to correct a raster distortion; a powersupply for developing a supply current of said main deflection circuitand a positive and a negative supply voltage of said first amplifierstage, said power supply developing said positive supply voltage beforedeveloping said negative supply voltage; a sensor for detecting anoccurrence a fault condition in a current path of said power supplycurrent of first amplifier stage; and a first power switch responsive toan output of said sensor for disconnecting said power supply voltages ofsaid first amplifier stage, without interrupting said supply current ofsaid main deflection circuit, when said fault condition occurs.
 2. Thevideo display apparatus according to claim 1 wherein said first powerswitch decouples said first amplifer stage from said power supply, whensaid fault condition occurs.
 3. The video display apparatus according toclaim 1 wherein said main deflection winding comprises one of a verticaldeflection winding and a horizontal deflection winding and wherein saidauxiliary winding comprises a convergence winding.
 4. The video displayapparatus according to claim 1 wherein said main deflection circuitcomprises an output stage of said deflection circuit.
 5. The videodisplay apparatus according to claim 4 wherein said output stage of saiddeflection circuit continues operating and said first amplifier stageceases generating said auxiliary deflection current, when said faultcondition occurs.
 6. The video display apparatus according to claim 1,further comprising a second amplifier stage for generating a portion ofsaid auxiliary deflection current, a transformer coupled to said powersupply for generating a third power supply current of said secondamplifier stage and a second power switch responsive to a control signalthat is produced in said first amplifier stage for decoupling, inaccordance with said control signal, said second amplifier stage fromsaid transformer, when said first fault condition occurs.